The present invention relates to a nonvolatile semiconductor memory device to be electrically programmed or erased, and an erasing method thereof.
Recently, various kinds of flash memories using a cell transistor with a floating gate structure have been proposed. This kind of a flash memory can be programmed or erased by providing a thin insulating film of about 10 nm between a substrate and a floating gate, and injecting or pulling out electrons to or from the floating gate via the insulating film. As a flash memory, the NOR type and the NAND type have already been developed. The NAND type flash memory is advantageous in that the size of the memory cell can be smaller to realize a lower cost compared with the NOR type. Since the NAND type flash memory needs little electric current in writing, memory cells of several k-bit can be programmed at the same time so that a high programming speed can be realized. Concerning the NAND type flash memory, various articles have been known. Examples thereof include the U.S. Pat. No. 5,297,029 by the present inventor, which discloses the basic operations such as reading, writing and erasing.
FIG. 1 is a circuit diagram schematically showing the memory cell in the above-mentioned NAND type flash memory and a surrounding circuit section relating to the reading operation.
In the NAND type flash memory, electric current paths of a plurality of memory cells MC1 to MCn are connected in series. To the source end and the drain end of the series-connected electric current path, a source select gate (select transistor) ST1 and a drain select gate (select transistor) ST2 are connected, respectively with a plurality of NAND bundles 11. The source end of the electric current path at the NAND bundle 11 is connected to a power source Vss and the drain end is connected to a bitline BL, respectively. An electric current path of a pre-charge transistor PT to be on/off controlled by a signal SA is connected between the bitline BL and a voltage supply source VPR. One end of an electric current path of a transistor DT to be on/off controlled by a signal SB is connected to the bitline BL. The other end of the electric current path of the transistor DT is connected to a sense amplifier resister circuit 16 comprising an inverter INV1 and an inverter INV2.
Although it is not illustrated, a plurality of NAND bundles are connected to the above-mentioned bitline BL in the row direction, and a plurality of bitlines are connected thereto in the column direction. To each of the bitlines, a plurality of NAND bundles are connected in the row direction. As in FIG. 1, a precharge transistor PT, a transistor DT and a sense amplifier and register circuit 16 are connected to each bitline.
To a control gate of each memory cell MC1 to MCn in the NAND bundle 11, word lines WL1 to WLn arranged normal to the bitline BL are connected per row. To the gate of each select transistor ST1, ST2, select lines SGS, SGD are connected per row. By applying a power source voltage Vcc to the select lines SGS, SGD, the select transistors ST1, ST2 are switched on, and a group of the NAND bundles arranged in the column direction is selected. To a selected word line WLm (m denotes any of 1 to n), 0 V is applied and to a non-selected word line in the NAND bundles, the power source voltage Vcc is applied. In other words, 0 V is applied to the control gate of the selected memory cell, and the power source voltage Vcc is applied to the control gate of the non-selected memory cell, respectively. Accordingly, if the threshold voltage of the selected memory cell is positive, the memory cell is in the off state, and if it is negative, the memory cell is in the on state. On the other hand, 0 V is supplied to the control gate of the non-selected memory cell in the NAND bundles and to the gate of the non-selected select transistor, respectively.
In the above-mentioned configuration, the read operation is carried out as shown in the timing chart of FIG. 2.
When starting the read (time t0), the signal SA is at the "H" level (at this time the signal SB is at the "L" level), the precharge transistor PT is in the on state, and the transistor DT is in the off state so that the bitline BL is precharged by the voltage supply source VPR. Then in the period between the signal SA is at the "L" level and the precharge transistor PT becomes off at the time t1, and the signal SB is at the "H" level and the transistor DT becomes at on state at the time t2, the potential of the bitline BL changes according to the threshold voltage (according to whether the selected memory cell is in the write state of the erase state) of the selected memory cell. When the signal SB becomes "H" level at the time t2, the transistor DT becomes at on state so that the bitline BL and the sense amplifier and register circuit 16 are connected to amplify the potential of the bitline BL to be latched to the sense amplifier and register circuit 16.
When electrons are injected to the floating gate of the selected memory cell MCm (write state), the threshold voltage of the memory cell MCm becomes high so that the memory cell MCm maintains the off state. Accordingly, the electric current does not flow from the bitline BL to the power source Vss via the selected NAND bundles so that the potential of the bitline BL does not lower. On the other hand, since the threshold voltage of the selected memory cell MCm is low when electrons are pulled out from the floating gate (erase state), the MCm is in the on state (at this time, a non-selected memory cell is also on). Accordingly, the electric current flows from the bitline BL to the power source Vs via the selected NAND bundles so that the potential of the bitline BL lowers. The potential of the bitline BL at the time t2 is supplied to the sense amplifier register circuit 16 so as to be latched as the memory data of the selected memory cell MCm.
Herein the operation until the memory data of the memory cell MCm is latched to the sense amplifier register circuit 16 is defined as the page read operation.
Usually, a sense amplifier register circuit 16 is connected to each bitline BL. In the case of a 16 Mbit NAND type EEPROM, about 2,000 pieces of the sense amplifier register circuits 16 are provided. The read operation of the data of the memory cell stored in the sense amplifier register circuit 16 to the outside is referred to as the serial read operation. By selectively switching on the column gate transistor (not illustrated) connected to the sense amplifier register circuit 16, the content of the sense amplifier register circuit 16 at a certain address can be read out to the outside.
In the above-mentioned NAND type flash memory, it is known that by the repetition of the programming and erase operations, electrons are trapped in the insulating film under the floating gate so that the threshold voltage of the memory cell after erasure becomes shallow (approaches to 0 V). FIG. 3 shows the result of dependency of the threshold voltage after erasure of a memory cell with respect to the number of programming/erase operations. From FIG. 3, it is leaned that the threshold voltage of the memory cell after the erase operation rises from about 100,000 times of the programming/erase operations, and the tendency becomes conspicuous from about 1,000,000 times. Therefore, after the 1,000,000 times programming/erase operations, in order to erase to the threshold voltage level the same as the up to 100,000 times level, the erase time needs to be longer. Accordingly, a conventional NAND type flash memory has a problem in that if programming and erase operations are repeated until the region where the oxide film of the memory cell wears the erase time becomes extremely long and thus actually it cannot be used until 1,000,000 times.
FIG. 4 shows the relationship between the threshold voltage of a memory cell after erasure and the page read time.
Usually, a bitline has a capacity of about several pF, and the read time is determined according to the speed of discharging the capacity. The discharge speed depends on the threshold voltage of the memory cell in the erase state. Therefore, by setting the read speed slower, even a little cell electric current can discharge the bitline charge of about several pF so that even a memory cell with a shallow threshold voltage can be judged as in the erase state. On the other hand, by setting the read speed faster, much cell electric current is required for the bitline charge discharge so that a deep threshold voltage is needed to be judged as in the erase state.
As mentioned above, in order not to have the erase time longer even after 1,000,000 times of writing and erasure, the read time can be set longer so that a memory cell with a shallow threshold voltage can be regarded as in the erase state. However, it involves a problem in that if the read speed is set to be slow in advance according to the shallow threshold voltage after 1,000,000 times programming and erasure, the access time to the memory chip becomes longer so that the performance of the NAND type flash memory is deteriorated.
As heretofore mentioned, conventional nonvolatile semiconductor memory device and erasing method thereof have a problem in that the threshold voltage of the memory cell after erasure becomes shallow after the repetition of programming and erase operations so as to dramatically prolong the erase time.